High-end ATE’s are designed to detect functional and AC/DC parametric failures but cannot identify or pinpoint potential in-system failures. Most in-system failures are a result of functional and timing compatibility issues that are generated by the system chipset. Many in-system device failures occur during system boot up or during performance of a specific operation within a given system.

To effectively deal with functional testing as well as in-system compatibility testing, most memory manufacturers incorporate a costly two (2) step testing process as part of their Standard Operating Procedure (S.O.P.)

1.  Functional and parametric testing
2.  In-System testing utilizing motherboards

One of the most difficult challenges facing memory manufacturers is finding a cost effective method of testing their products so they can minimize time to market and field failures/returns. To facilitate this costly and time consuming process they must incorporate the two (2) step testing process. Capital expenditures, for the equipment and manpower required to do this extensive testing, often result in budget overruns for various cost centers.

To assist manufacturers in their efforts to control costs, Triad Spectrum proudly introduces the TCIII-1333ST multi-site test system.

Device characterization and failure analysis tools such as Schmoo plotting and address/data error logging are included on the TCIII-1333ST to assist engineers in their design/debug processes. An optional hot temperature chamber is available to detect marginal timing and cell storage failures that often occur in high temperature system environments. The chamber is user programmable and can be set at temperatures ranging from 32°C to 85°C with 2°C resolution .

Bitmap is a tool that helps users to find and display the failed DQ bits in the DRAM IC. The corresponding row and column address of the failed DQ bits will be spotted and displayed for the user with the aid of the diagrams. First, for example, the failed Bank is spotted (Figure 1). After that, the user can find the location of the failed DQ bit (Figure 2) if the user double-clicks the failed Bank.

This will detect shorts on the signal line as well as detect proper values of resistor packs and discreet resistors to insure that proper values are used in all places as well as insuring that they are properly mounted.

A pattern that will detect any "open pins" on the contacts in between test sockets and DIMM’s before functional testing begins. This pattern will also detect any open pins on both passive and memory components on the PCB.

Shorts ranging from 0 Ohm up to 600 Ohms will be detected on the DUT.

Voltage ref short detection including programmable VrefCA and VrefDQ.